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9S12A128DGV1/D 4/2002
MC9S12A128 Device Guide V01.01
Original Release Date: 8 March, 2002 Revised: 17 April, 2002
Motorola, Inc
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
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MC9S12A128 Device Guide -- V01.01
Revision History
Version Revision Effective Number Date Date
V01.00 8 MAR 2002 8 MAR 2002
Author
Initial release
Description of Changes
Replaced document order number with version except for cover sheet Corrected Table 1-1 Device Memory Map entries for EEPROM array and RAM array V01.01 17 APRIL 2002 12 APRIL 2002 Table A-4 Operating Conditions -- Increased VDD to 2.35V Table A-6 5V I/O Characteristics -- Corrected rating column for VOH and VOL and typical value for Cin Table A-8 ATD Operating Characteristics -- Updated rating definitions for items 6, 7, and 8 for clarity
For additional information, refer to the MC9S12A128 8-Bit Microcontroller Unit Mask Set Errata (Motorola document order number, 9S12A128MSE1). The errata can be found on the World Wide Web at: http://www.motorola.com/semiconductors/
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MC9S12A128 Device Guide -- V01.01
Table of Contents
Section 1 Introduction
1.1 1.2 1.3 1.4 1.5 1.6 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Section 2 Signal Description
2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.3 Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.3.1 EXTAL, XTAL -- Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.3.2 RESET -- External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.3.3 TEST -- Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.3.4 VREGEN -- Voltage Regulator Enable Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.3.5 XFC -- PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.3.6 BKGD / TAGHI / MODC -- Background Debug, Tag High, and Mode Pin . . . . . . . . 29 2.3.7 PAD15 / AN15 / ETRIG1 -- Port AD Input Pin of ATD1 . . . . . . . . . . . . . . . . . . . . . . 29 2.3.8 PAD[14:08] / AN[14:08] -- Port AD Input Pins of ATD1 . . . . . . . . . . . . . . . . . . . . . . 29 2.3.9 PAD7 / AN07 / ETRIG0 -- Port AD Input Pin of ATD0 . . . . . . . . . . . . . . . . . . . . . . . 29 2.3.10 PAD[06:00] / AN[06:00] -- Port AD Input Pins of ATD0 . . . . . . . . . . . . . . . . . . . . . . 29 2.3.11 PA[7:0] / ADDR[15:8] / DATA[15:8] -- Port A I/O Pins . . . . . . . . . . . . . . . . . . . . . . . 29 2.3.12 PB[7:0] / ADDR[7:0] / DATA[7:0] -- Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.3.13 PE7 / NOACC / XCLKS -- Port E I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.3.14 PE6 / MODB / IPIPE1 -- Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.3.15 PE5 / MODA / IPIPE0 -- Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.3.16 PE4 / ECLK -- Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.3.17 PE3 / LSTRB / TAGLO -- Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.3.18 PE2 / R/W -- Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.3.19 PE1 / IRQ -- Port E Input Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.3.20 PE0 / XIRQ -- Port E Input Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.3.21 PH7 / KWH7 -- Port H I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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MC9S12A128 Device Guide -- V01.01
2.3.22 2.3.23 2.3.24 2.3.25 2.3.26 2.3.27 2.3.28 2.3.29 2.3.30 2.3.31 2.3.32 2.3.33 2.3.34 2.3.35 2.3.36 2.3.37 2.3.38 2.3.39 2.3.40 2.3.41 2.3.42 2.3.43 2.3.44 2.3.45 2.3.46 2.3.47 2.3.48 2.3.49 2.3.50 2.3.51 2.3.52 2.3.53 2.3.54 2.3.55 2.3.56 2.3.57
PH6 / KWH6 -- Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PH5 / KWH5 -- Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PH4 / KWH4 -- Port H I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PH3 / KWH3 / SS1 -- Port H I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PH2 / KWH2 / SCK1 -- Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PH1 / KWH1 / MOSI1 -- Port H I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 PH0 / KWH0 / MISO1 -- Port H I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 PJ7 / KWJ7 / SCL -- PORT J I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PJ6 / KWJ6 / SDA -- PORT J I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PJ[1:0] / KWJ[1:0] -- Port J I/O Pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 PK7 / ECS / ROMON -- Port K I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 PK[5:0] / XADDR[19:14] -- Port K I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PM7 -- Port M I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PM6 -- Port M I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PM5 / SCK0 -- Port M I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PM4 / MOSI0 -- Port M I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PM3 / SS0 -- Port M I/O Pin 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 PM2 / MISO0 -- Port M I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 PM1 -- Port M I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 PM0 -- Port M I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 PP7 / KWP7 / PWM7 -- Port P I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 PP6 / KWP6 / PWM6 -- Port P I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 PP5 / KWP5 / PWM5 -- Port P I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 PP4 / KWP4 / PWM4 -- Port P I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 PP3 / KWP3 / PWM3 / SS1 -- Port P I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 PP2 / KWP2 / PWM2 / SCK1 -- Port P I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PP1 / KWP1 / PWM1 / MOSI1 -- Port P I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PP0 / KWP0 / PWM0 / MISO1 -- Port P I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PS7 / SS0 -- Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PS6 / SCK0 -- Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PS5 / MOSI0 -- Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PS4 / MISO0 -- Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PS3 / TXD1 -- Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PS2 / RXD1 -- Port S I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 PS1 / TXD0 -- Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 PS0 / RXD0 -- Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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MC9S12A128 Device Guide -- V01.01
2.3.58 PT[7:0] / IOC[7:0] -- Port T I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.4.1 VDDX, VSSX -- Power & Ground Pins for I/O Drivers . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.4.2 VDDR, VSSR -- Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.4.3 2.4.4 2.4.5 2.4.6 2.4.7 VDD1, VDD2, VSS1, VSS2 -- Core Power Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 VDDA, VSSA -- Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . . . . . . 36 VRH, VRL -- ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 VDDPLL, VSSPLL -- Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 VREGEN -- On Chip Voltage Regulator Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Section 3 System Clock Description
3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Section 4 Modes of Operation
4.1 4.2 4.2.1 4.2.2 4.2.3 4.3 4.3.1 4.3.2 4.3.3 4.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Normal Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Special Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Test Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Section 5 Resets and Interrupts
5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 5.2.1 Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.3.1 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.3.2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Section 6 HCS12 Core Block Description Section 7 Clock and Reset Generator (CRG) Block Description
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7.1 Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.1.1 XCLKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Section 8 Enhanced Capture Timer (ECT) Block Description Section 9 Analog to Digital Converter (ATD) Block Description Section 10 Inter-IC Bus (IIC) Block Description Section 11 Serial Communications Interface (SCI) Block Description Section 12 Serial Peripheral Interface (SPI) Block Description Section 13 Pulse Width Modulator (PWM) Block Description Section 14 Flash EEPROM 128K Block Description Section 15 EEPROM 2K Block Description Section 16 RAM Block Description Section 17 Port Integration Module (PIM) Block Description Section 18 Voltage Regulator (VREG) Block Description Appendix A Electrical Characteristics
A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 A.1.4 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 A.1.6 ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
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A.2 A.2.1 A.2.2 A.2.3 A.3 A.3.1 A.3.2 A.4 A.5 A.5.1 A.5.2 A.5.3 A.6 A.6.1 A.6.2 A.7 A.7.1
ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Factors Influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 ATD Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 NVM, Flash, and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 NVM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Voltage Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 General Muxed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Appendix B Package Information
B.1 B.2 B.3 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 112-Pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 80-Pin QFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
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List of Figures
Figure 1-1 Figure 1-2 Figure 2-1 Figure 2-2 Figure 2-3 Figure 3-1 Figure 18-1 Figure 18-2 Figure A-1 Figure A-2 Figure A-3 Figure A-4 Figure A-5 Figure A-6 Figure A-7 Figure A-8 Figure A-9 Figure B-1 Figure B-2 MC9S12A128 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 MC9S12A128 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Pin Assignments in 112-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Pin Assignments in 80-Pin QFP for MC9S12A128 . . . . . . . . . . . . . . . . . . . . . . . 25 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Recommended PCB Layout 112 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Recommended PCB Layout for 80 QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Basic PLL Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Maximum Bus Clock Jitter Approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 SPI Master Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 SPI Slave Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 112-Pin LQFP Mechanical Dimensions (Case no. 987) . . . . . . . . . . . . . . . . . . 88 80-pin QFP Mechanical Dimensions (Case no. 841B) . . . . . . . . . . . . . . . . . . . 89
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List of Tables
Table 0-1 Table 1-1 Table 1-2 Table 1-3 Table 2-1 Table 2-2 Table 4-1 Table 5-1 Table A-1 Table A-2 Table A-3 Table A-4 Table A-5 Table A-6 Table A-7 Table A-8 Table A-9 Table A-10 Table A-11 Table A-12 Table A-13 Table A-14 Table A-15 Table A-16 Table A-17 Table A-18 Table A-19 Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Memory Size Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 MC9S12A128 Power and Ground Connection Summary . . . . . . . . . . . . . . . . . . .37 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 ESD and Latch-Up Protection Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 ATD Conversion Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 NVM Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Voltage Regulator Recommended Load Capacitances . . . . . . . . . . . . . . . . . . . . 73 Startup Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 PLL Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 SPI Slave Mode Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Expanded Bus Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
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Preface
The Device User Guide provides information about the MC9S12A128 device made up of standard HCS12 blocks and the HCS12 processor core. This document is part of the customer documentation. A complete set of device manuals also includes the CPU12 Reference Manual (Motorola order number, CPU12RM/AD) and all the individual Block Guides of the implemented modules. In a effort to reduce redundancy all module specific information is located only in the respective Block Guide. If applicable, special implementation details of the module are given in the block description sections of this document. See Table 0-1 for names and versions of the referenced documents throughout the Device Guide.
Table 0-1 Document References
User Guide
HCS12 Core User Guide CRG Block Guide ECT_16B8C Block Guide ATD_10B8C Block Guide IIC Block Guide SCI Block Guide SPI Block Guide PWM_8B8C Block Guide FTS128K Block Guide EETS2K Block Guide VREG Block Guide PIM_9A128 Block Guide
Version
V01 V03 V01 V02 V02 V02 V02 V01 V02 V02 V01 V01
Document Order Number
HCS12COREUG/D S12CRGV3/D S12ECT16B8CV1/D S12ATD10B8CV2/D S12IICV2/D S12SCIV2/D S12SPIV2/D S12PWM8B8CV1/D S12FTS128KV1/D S12EETS2KV1/D S12VREGV1/D S12A128PIMV1/D
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Section 1 Introduction
1.1 Overview
The MC9S12A128 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (HCS12 CPU), 128K bytes of Flash EEPROM, 8K bytes of RAM, 2K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), two serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, two 8-channel, 10-bit analog-to-digital converters (ADC), an 8-channel pulse-width modulator (PWM), 29 discrete digital I/O channels (Port A, Port B, Port K and Port E), 20 discrete digital I/O lines with interrupt and wakeup capability and an Inter-IC Bus. System resource mapping, clock generation, interrupt control and bus interfacing are managed by the System Integration Module (SIM). The MC9S12A128 has full 16-bit data paths throughout. However, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements.
1.2 Features
* HCS12 Core - 16-bit HCS12 CPU i. Upward compatible with M68HC11 instruction set ii. Interrupt stacking and programmer's model identical to M68HC11 iii. Instruction queue iv. Enhanced indexed addressing - - - - - * * MEBI (Multiplexed External Bus Interface) MMC (Module Mapping Control) INT (Interrupt control) BKP (Breakpoints) BDM (Background Debug Mode)
CRG (low current oscillator, PLL, reset, clocks, COP watchdog, real time interrupt, clock monitor) 8-bit and 4-bit ports with interrupt functionality - - Digital filtering Programmable rising or falling edge trigger 128K Flash EEPROM 2K byte EEPROM 8K byte RAM
*
Memory - - -
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*
Two 8-channel Analog-to-Digital Converters - - 10-bit resolution External conversion trigger capability 16-bit main counter with 7-bit prescaler 8 programmable input capture or output compare channels Two 8-bit or one 16-bit pulse accumulators Programmable period and duty cycle 8-bit 8-channel or 16-bit 4-channel Separate control for each pulse width and duty cycle Center-aligned or left-aligned outputs Programmable clock select logic with a wide range of frequencies Fast emergency shutdown input Usable as interrupt inputs Two asynchronous Serial Communications Interfaces (SCI) Two Synchronous Serial Peripheral Interface (SPI) Compatible with I2C Bus standard Multi-master operation Software programmable for one of 256 different serial clock frequencies I/O lines with 5V input and drive capability 5V A/D converter inputs Operation at 50MHz equivalent to 25MHz Bus Speed Development support Single-wire background debugTM mode (BDM) On-chip hardware breakpoints
*
Enhanced Capture Timer - - -
*
8 PWM channels - - - - - - -
*
Serial interfaces - -
*
Inter-IC Bus (IIC) - - -
*
112-Pin LQFP and 80-pin QFP packages - - - - - -
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1.3 Modes of Operation
User modes * Normal and Emulation Operating Modes - - - - - * - - - Normal Single-Chip Mode Normal Expanded Wide Mode Normal Expanded Narrow Mode Emulation Expanded Wide Mode Emulation Expanded Narrow Mode Special Single-Chip Mode with active Background Debug Mode Special Test Mode (Motorola use only) Special Peripheral Mode (Motorola use only)
Special Operating Modes
Low power modes * * * Stop Mode Pseudo Stop Mode Wait Mode
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1.4 Block Diagram
Figure 1-1 shows a block diagram of the MC9S12A128 device.
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Figure 1-1 MC9S12A128 Block Diagram
128K Byte Flash EEPROM 8K Byte RAM 2K Byte EEPROM
VDDR VSSR VREGEN VDD1,2 VSS1,2 BKGD XFC VDDPLL VSSPLL EXTAL XTAL RESET PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 TEST AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
ATD0
VRH VRL VDDA VSSA PAD00 PAD01 PAD02 PAD03 PAD04 PAD05 PAD06 PAD07
ATD1
VRH VRL VDDA VSSA
VRH VRL VDDA VSSA PAD08 PAD09 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PK0 PK1 PK2 PK3 PK4 PK5 PK7 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PM0 PM1 PM2 PM3 PM4 PM5 PM6 PM7 XADDR14 XADDR15 XADDR16 XADDR17 XADDR18 XADDR19
Voltage Regulator
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 PIX0 PIX1 PIX2 PIX3 PIX4 PIX5 ECS IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 RXD TXD RXD TXD
AD0
Single-wire Background Debug Module
Clock and Reset Generation Module
CPU12
DDRK
PPAGE
PLL
Periodic Interrupt COP Watchdog Clock Monitor Breakpoints
PTK
AD1
ECS
XIRQ IRQ System R/W Integration LSTRB Module ECLK (SIM) MODA MODB NOACC/XCLKS
DDRE
PTE
Enhanced Capture Timer
DDRT DDRS
SCI0 SCI1
PTS
PTT
Multiplexed Address/Data Bus SPI0 DDRA PTA
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
MISO MOSI SCK SS
DDRB Module to Port Routing PTB
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
Multiplexed Wide Bus
IIC
SDA SCL PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 MISO MOSI SCK SS
Internal Logic 2.5V
VDD1,2 VSS1,2
I/O Driver 5V
VDDX VSSX
PTJ
Multiplexed Narrow Bus
KWJ0 KWJ1 KWJ6 KWJ7 KWP0 KWP1 KWP2 KWP3 KWP4 KWP5 KWP6 KWP7 KWH0 KWH1 KWH2 KWH3 KWH4 KWH5 KWH6 KWH7
PJ0 PJ1 PJ6 PJ7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
DDRP
DDRJ
PLL 2.5V
VDDPLL VSSPLL
A/D Converter 5V & Voltage Regulator Reference
VDDA VSSA
PWM
Voltage Regulator 5V & I/O
VDDR VSSR
SPI1
DDRH
PTH
PTP
Signals shown in Bold are not available on the 80 Pin Package
DDRM
ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8
DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
PTM
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1.5 Device Memory Map
Table 1-1 and Figure 1-2 show the device memory map of the MC9S12A128 after reset. Note that after reset the bottom 1K of the EEPROM ($0000 - $03FF) are hidden by the register space. Table 1-1 Device Memory Map
Address
$0000 - $0017 $0018 - $0019
Module
CORE (Ports A, B, E, Modes, Inits, Test) Reserved
Size (Bytes)
24 2 2 4 8 8 4 12 64 32 40 8 8 8 8 8 8 8 16 12 4 32 256 64 384 2048 8192 16384 16384 16384
$001A - $001B Device ID register (PARTID) $001C - $001F CORE (MEMSIZ, IRQ, HPRIO) $0020 - $0027 $0030 - $0033 Reserved CORE (PPAGE, Port K) $0028 - $002F CORE (Background Debug Mode) $0034 - $003F Clock and Reset Generator (PLL, RTI, COP) $0040 - $007F Enhanced Capture Timer 16-bit 8 channels $0080 - $009F Analog to Digital Converter 10-bit 8 channels (ATD0) $00A0 - $00C7 Pulse Width Modulator 8-bit 8 channels (PWM) $00C8 - $00CF Serial Communications Interface 0 (SCI0) $00D0 - $00D7 Serial Communications Interface 0 (SCI1) $00D8 - $00DF Serial Peripheral Interface (SPI0) $00E0 - $00E7 Inter IC Bus $00E8 - $00EF Reserved $00F0 - $00F7 Serial Peripheral Interface (SPI1) $00F8 - $00FF Reserved $0100- $010F $0110 - $011B Flash Control Register EEPROM Control Register
$011C - $011F Reserved $0120 - $013F Analog to Digital Converter 10-bit 8 channels (ATD1) $0140 - $023F Reserved $0240 - $027F Port Integration Module (PIM) $0280 - $03FF Reserved $0000 - $07FF EEPROM array $0000 - $1FFF RAM array $4000 - $7FFF Fixed Flash EEPROM array incl. 0.5K, 1K, 2K or 4K Protected Sector at start
$8000 - $BFFF Flash EEPROM Page Window Fixed Flash EEPROM array $C000 - $FFFF incl. 0.5K, 1K, 2K or 4K Protected Sector at end and 256 bytes of Vector Space at $FF80 - $FFFF
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Figure 1-2 MC9S12A128 Memory Map
$0000 $0000 $0400 $0800 $1000 $2000 $03FF $0800 $0FFF $2000 $3FFF $4000 $4000 0.5K, 1K, 2K or 4K Protected Sector 1K Register Space Mappable to any 2K Boundary 2K Bytes EEPROM Mappable to any 2K Boundary 8K Bytes RAM Mappable to any 8K Boundary
$7FFF $8000 $8000 EXT $BFFF $C000 $C000
16K Fixed Flash EEPROM
16K Page Window eight * 16K Flash EEPROM Pages
16K Fixed Flash EEPROM
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
2K, 4K, 8K or 16K Protected Boot Sector BDM (If Active)
The address does not show the map after reset, but a useful map. After reset the map is: $0000 - $03FF: Register Space $0000 - $1FFF: 8K RAM $0000 - $07FF: 2K EEPROM (not visible) $2000 - $3FFF: 8K Flash
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1.6 Part ID Assignments
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B after reset). The read-only value is a unique part ID for each revision of the chip. Table 1-2 shows the assigned part ID number. Table 1-2 Assigned Part ID Numbers
Device MC9S12A128 Mask Set Number 0L85D Part ID1 $0100
NOTES: 1. The coding is as follows: Bit 15-12: Major family identifier Bit 11-8: Minor family identifier Bit 7-4: Major mask set revision number including FAB transfers Bit 3-0: Minor - non full - mask set revision
The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses $001C and $001D after reset). Table 1-3 shows the read-only values of these registers. Refer to the HCS12 Core User Guide (Motorola document order number HCS12COREUG/D) for further details.
Table 1-3 Memory Size Registers
Register name MEMSIZ0 MEMSIZ1 Value $13 $80
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Section 2 Signal Description
This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. It is built from the signal description sections of the Block Guides of the individual IP blocks on the device.
2.1 Device Pinout
The MC9S12A128 is available in a 112-pin low profile quad flat pack (LQFP) and is also available in a 80-pin quad flat pack (QFP). Most pins perform two or more functions, as described in the 2.3 Detailed Signal Descriptions. Figure 2-1 and Figure 2-2 show the pin assignments.
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ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 KWH7/PH7 KWH6/PH6 KWH5/PH5 KWH4/PH4 XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST SS1/KWH3/PH3 SCK1/KWH2/PH2 MOSI1/KWH1/PH1 MISO1/KWH0/PH0 LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0 XADDR17/PK3 XADDR16/PK2 XADDR15/PK1 XADDR14/PK0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 XADDR19/PK5 XADDR18/PK4 KWJ1/PJ1 KWJ0/PJ0 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
PP4/KWP4/PWM4 PP5/KPW5/PWM5 PP6/KWP6/PWM6 PP7/KWP7/PWM7 PK7/ECS VDDX VSSX PM0 PM1 PM2/MISO0 PM3/SS0 PM4/MOSI PM5/SCK0 PJ6/KWJ6/SDA PJ7/KWJ7/SCL VREGEN PS7/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 PM6 PM7 VSSA VRL 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
MC9S12A128
VRH VDDA PAD15/AN15/ETRIG1 PAD07/AN07/ETRIG0 PAD14/AN14 PAD06/AN06 PAD13/AN13 PAD05/AN05 PAD12/AN12 PAD04/AN04 PAD11/AN11 PAD03/AN03 PAD10/AN10 PAD02/AN02 PAD09/AN09 PAD01/AN01 PAD08/AN08 PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8
Signals shown in Bold are not available on the 80 Pin Package
Figure 2-1 Pin Assignments in 112-Pin LQFP
MC9S12A128 Device Guide -- V01.01
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
PP4/KWP4/PWM4 PP5/KWP5/PWM5 PP7/KWP7/PWM7 VDDX VSSX PM0 PM1 PM2/MISO0 PM3/SS0 PM4/MOSI0 PM5/SCK0 PJ6/KWJ6/SDA PJ7/KWJ7/SCL VREGEN PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VRL SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
MC9S12A128
VRH VDDA PAD07/AN07/ETRIG0 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8
Figure 2-2 Pin Assignments in 80-Pin QFP for MC9S12A128
ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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2.2 Signal Properties Summary
Table 2-1 summarizes the pin functionality. Signals shown in bold are not available in the 80 pin package. Table 2-1 Signal Properties
Pin Name Function 1
EXTAL XTAL RESET TEST VREGEN XFC BKGD PAD15 PAD[14:8] PAD07 PAD[06:00] PA[7:0] PB[7:0] PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0
Pin Name Function 2
-- -- -- -- -- -- TAGHI AN15 AN[14:08] AN07 AN[06:00] ADDR[15:8]/ DATA[15:8] ADDR[7:0]/ DATA[7:0] NOACC IPIPE1 IPIPE0 ECLK LSTRB R/W IRQ XIRQ KWH7 KWH6 KWH5 KWH4 KWH3 KWH2 KWH1 KWH0
Pin Name Function 3
-- -- -- -- -- -- MODC ETRIG1 -- ETRIG0 -- -- -- XCLKS MODB MODA -- TAGLO -- -- -- -- -- -- -- SS1 SCK1 MOSI1 MISO1
Pin Name Function 4
-- -- -- -- -- -- -- -- --
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VDDPLL VDDR N.A. VDDX VDDPLL VDDR Oscillator Pins
Description
External Reset Test Input Voltage Regulator Enable Input PLL Loop Filter Background Debug, Tag High, Mode Input Port AD Input, Analog Input AN7 of ATD1, External Trigger Input of ATD1 Port AD Inputs, Analog Inputs AN[6:0] of ATD1 Port AD Input, Analog Input AN7 of ATD0, External Trigger Input of ATD0 Port AD Inputs, Analog Inputs AN[6:0] of ATD0 Port A I/O, Multiplexed Address/Data Port B I/O, Multiplexed Address/Data Port E I/O, Access, Clock Select Port E I/O, Pipe Status, Mode Input Port E I/O, Pipe Status, Mode Input Port E I/O, Bus Clock Output Port E I/O, Byte Strobe, Tag Low Port E I/O, R/W in expanded modes
VDDA -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VDDR
Port E Input, Maskable Interrupt Port E Input, Non Maskable Interrupt Port H I/O, Interrupt Port H I/O, Interrupt Port H I/O, Interrupt Port H I/O, Interrupt Port H I/O, Interrupt, SS of SPI1 Port H I/O, Interrupt, SCK of SPI1 Port H I/O, Interrupt, MOSI of SPI1 Port H I/O, Interrupt, MISO of SPI1
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MC9S12A128 Device Guide -- V01.01 Pin Name Function 1
PJ7 PJ6 PJ[1:0] PK7 PK[5:0] PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0 PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 PT[7:0]
Pin Name Function 2
KWJ7 KWJ6 KWJ[1:0] ECS XADDR[19:14] -- -- SCK0 MOSI0 SS0 MISO0 -- -- KWP7 KWP6 KWP5 KWP4 KWP3 KWP2 KWP1 KWP0 SS0 SCK0 MOSI0 MISO0 TXD1 RXD1 TXD0 RXD0 IOC[7:0]
Pin Name Function 3
SCL SDA -- ROMON
Pin Name Function 4
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Description
Port J I/O, Interrupt, SCL of IIC Port J I/O, Interrupt, SDA of IIC
-- -- --
Port J I/O, Interrupts Port K I/O, Emulation Chip Select, ROM On Enable Port K I/O, Extended Addresses Port M I/O Port M I/O Port M I/O, SCK of SPI0 Port M I/O, MOSI of SPI0 Port M I/O, SS of SPI0 Port M I/O, MISO of SPI0 Port M I/O Port M I/O Port P I/O, Interrupt, Channel 7 of PWM Port P I/O, Interrupt, Channel 6 of PWM Port P I/O, Interrupt, Channel 5 of PWM VDDX Port P I/O, Interrupt, Channel 4 of PWM Port P I/O, Interrupt, Channel 3 of PWM, SS of SPI1 Port P I/O, Interrupt, Channel 2 of PWM, SCK of SPI1 Port P I/O, Interrupt, Channel 1 of PWM, MOSI of SPI1 Port P I/O, Interrupt, Channel 0 of PWM, MISO of SPI1 Port S I/O, SS of SPI0 Port S I/O, SCK of SPI0 Port S I/O, MOSI of SPI0 Port S I/O, MISO of SPI0 Port S I/O, TXD of SCI1 Port S I/O, RXD of SCI1 Port S I/O, TXD of SCI0 Port S I/O, RXD of SCI0 Port T I/O, Timer channels
-- -- -- -- -- -- -- -- PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- SS1 SCK1 MOSI1 MISO1 -- -- -- -- -- -- -- -- --
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2.3 Detailed Signal Descriptions
2.3.1 EXTAL, XTAL -- Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived from the EXTAL input frequency. XTAL is the crystal output.
2.3.2 RESET -- External Reset Pin
An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset.
2.3.3 TEST -- Test Pin
This input only pin is reserved for test. NOTE: The TEST pin must be tied to VSS in all applications.
2.3.4 VREGEN -- Voltage Regulator Enable Pin
This input only pin enables or disables the on-chip voltage regulator.
2.3.5 XFC -- PLL Loop Filter Pin
PLL loop filter, see A.5.3 Phase Locked Loop. If needed, contact your Motorola representative for the interactive application note to compute PLL loop filter elements. Any current leakage on this pin must be avoided.
XFC R0 MCU CS VDDPLL VDDPLL
CP
Figure 2-3 PLL Loop Filter Connections
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2.3.6 BKGD / TAGHI / MODC -- Background Debug, Tag High, and Mode Pin
The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug communication. In MCU expanded modes of operation when instruction tagging is on, an input low on this pin during the falling edge of E-clock tags the high half of the instruction word being read into the instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit at the rising edge of RESET.
2.3.7 PAD15 / AN15 / ETRIG1 -- Port AD Input Pin of ATD1
PAD15 is a general purpose input pin and analog input AN7 of the analog to digital converter ATD1. It can act as an external trigger input for the ATD1.
2.3.8 PAD[14:08] / AN[14:08] -- Port AD Input Pins of ATD1
PAD14 - PAD08 are general purpose input pins and analog inputs AN[6:0] of the analog to digital converter ATD1.
2.3.9 PAD7 / AN07 / ETRIG0 -- Port AD Input Pin of ATD0
PAD7 is a general purpose input pin and analog input AN7 of the analog to digital converter ATD0. It can act as an external trigger input for the ATD0.
2.3.10 PAD[06:00] / AN[06:00] -- Port AD Input Pins of ATD0
PAD06 - PAD00 are general purpose input pins and analog inputs AN[6:0] of the analog to digital converter ATD0.
2.3.11 PA[7:0] / ADDR[15:8] / DATA[15:8] -- Port A I/O Pins
PA7-PA0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus.
2.3.12 PB[7:0] / ADDR[7:0] / DATA[7:0] -- Port B I/O Pins
PB7-PB0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus.
2.3.13 PE7 / NOACC / XCLKS -- Port E I/O Pin 7
PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC signal, when enabled, is used to indicate that the current bus cycle is an unused or "free" cycle. This signal will assert when the CPU is not using the bus.
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The XCLKS input selects between an external clock or oscillator configuration. The state of this pin is latched at the rising edge of RESET. If the input is a logic low the EXTAL pin is configured for an external clock drive. If input is a logic high an oscillator circuit is configured on EXTAL and XTAL. Since this pin is an input with a pull-up device, if the pin is left floating, the default configuration is an oscillator circuit on EXTAL and XTAL.
2.3.14 PE6 / MODB / IPIPE1 -- Port E I/O Pin 6
PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE1. This pin is an input with a pull-down device which is only active when RESET is low.
2.3.15 PE5 / MODA / IPIPE0 -- Port E I/O Pin 5
PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE0. This pin is an input with a pull-down device which is only active when RESET is low.
2.3.16 PE4 / ECLK -- Port E I/O Pin 4
PE4 is a general purpose input or output pin. It can be configured to drive the internal bus clock ECLK. ECLK can be used as a timing reference.
2.3.17 PE3 / LSTRB / TAGLO -- Port E I/O Pin 3
PE3 is a general purpose input or output pin. In MCU expanded modes of operation, LSTRB can be used for the low-byte strobe function to indicate the type of bus access and when instruction tagging is on, TAGLO is used to tag the low half of the instruction word being read into the instruction queue.
2.3.18 PE2 / R/W -- Port E I/O Pin 2
PE2 is a general purpose input or output pin. In MCU expanded modes of operations, this pin drives the read/write output signal for the external bus. It indicates the direction of data on the external bus.
2.3.19 PE1 / IRQ -- Port E Input Pin 1
PE1 is a general purpose input pin and the maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
2.3.20 PE0 / XIRQ -- Port E Input Pin 0
PE0 is a general purpose input pin and the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
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2.3.21 PH7 / KWH7 -- Port H I/O Pin 7
PH7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.
2.3.22 PH6 / KWH6 -- Port H I/O Pin 6
PH6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.
2.3.23 PH5 / KWH5 -- Port H I/O Pin 5
PH5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.
2.3.24 PH4 / KWH4 -- Port H I/O Pin 4
PH4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.
2.3.25 PH3 / KWH3 / SS1 -- Port H I/O Pin 3
PH3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as slave select pin SS of the Serial Peripheral Interface 1 (SPI1).
2.3.26 PH2 / KWH2 / SCK1 -- Port H I/O Pin 2
PH2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as serial clock pin SCK of the Serial Peripheral Interface 1 (SPI1).
2.3.27 PH1 / KWH1 / MOSI1 -- Port H I/O Pin 1
PH1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 1 (SPI1).
2.3.28 PH0 / KWH0 / MISO1 -- Port H I/O Pin 0
PH0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of the Serial Peripheral Interface 1 (SPI1).
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2.3.29 PJ7 / KWJ7 / SCL -- PORT J I/O Pin 7
PJ7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as the serial clock pin SCL of the IIC module.
2.3.30 PJ6 / KWJ6 / SDA -- PORT J I/O Pin 6
PJ6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as the serial data pin SDA of the IIC module.
2.3.31 PJ[1:0] / KWJ[1:0] -- Port J I/O Pins [1:0]
PJ1 and PJ0 are general purpose input or output pins. They can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.
2.3.32 PK7 / ECS / ROMON -- Port K I/O Pin 7
PK7 is a general purpose input or output pin. During MCU expanded modes of operation, this pin is used as the emulation chip select output (ECS). During MCU normal expanded modes of operation, this pin is used to enable the Flash EEPROM memory in the memory map (ROMON). At the rising edge of RESET, the state of this pin is latched to the ROMON bit.
2.3.33 PK[5:0] / XADDR[19:14] -- Port K I/O Pins [5:0]
PK5-PK0 are general purpose input or output pins. In MCU expanded modes of operation, these pins provide the expanded address XADDR[19:14] for the external bus.
2.3.34 PM7 -- Port M I/O Pin 7
PM7 is a general purpose input or output pin.
2.3.35 PM6 -- Port M I/O Pin 6
PM6 is a general purpose input or output pin.
2.3.36 PM5 / SCK0 -- Port M I/O Pin 5
PM5 is a general purpose input or output pin. It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 (SPI0).
2.3.37 PM4 / MOSI0 -- Port M I/O Pin 4
PM4 is a general purpose input or output pin. It can be configured as the master output (during master mode) or slave input pin (during slave mode) MOSI for the Serial Peripheral Interface 0 (SPI0).
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2.3.38 PM3 / SS0 -- Port M I/O Pin 3
PM3 is a general purpose input or output pin. It can be configured as the slave select pin SS of the Serial Peripheral Interface 0 (SPI0).
2.3.39 PM2 / MISO0 -- Port M I/O Pin 2
PM2 is a general purpose input or output pin. It can be configured as the master input (during master mode) or slave output pin (during slave mode) MISO for the Serial Peripheral Interface 0 (SPI0).
2.3.40 PM1 -- Port M I/O Pin 1
PM1 is a general purpose input or output pin.
2.3.41 PM0 -- Port M I/O Pin 0
PM0 is a general purpose input or output pin.
2.3.42 PP7 / KWP7 / PWM7 -- Port P I/O Pin 7
PP7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 7 output.
2.3.43 PP6 / KWP6 / PWM6 -- Port P I/O Pin 6
PP6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 6 output.
2.3.44 PP5 / KWP5 / PWM5 -- Port P I/O Pin 5
PP5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 5 output.
2.3.45 PP4 / KWP4 / PWM4 -- Port P I/O Pin 4
PP4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 4 output
2.3.46 PP3 / KWP3 / PWM3 / SS1 -- Port P I/O Pin 3
PP3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 3 output. It can be configured as slave select pin SS of the Serial Peripheral Interface 1 (SPI1).
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2.3.47 PP2 / KWP2 / PWM2 / SCK1 -- Port P I/O Pin 2
PP2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 2 output. It can be configured as serial clock pin SCK of the Serial Peripheral Interface 1 (SPI1).
2.3.48 PP1 / KWP1 / PWM1 / MOSI1 -- Port P I/O Pin 1
PP1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 1 output. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 1 (SPI1).
2.3.49 PP0 / KWP0 / PWM0 / MISO1 -- Port P I/O Pin 0
PP0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 0 output. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of the Serial Peripheral Interface 1 (SPI1).
2.3.50 PS7 / SS0 -- Port S I/O Pin 7
PS7 is a general purpose input or output pin. It can be configured as the slave select pin SS of the Serial Peripheral Interface 0 (SPI0).
2.3.51 PS6 / SCK0 -- Port S I/O Pin 6
PS6 is a general purpose input or output pin. It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 (SPI0).
2.3.52 PS5 / MOSI0 -- Port S I/O Pin 5
PS5 is a general purpose input or output pin. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).
2.3.53 PS4 / MISO0 -- Port S I/O Pin 4
PS4 is a general purpose input or output pin. It can be configured as master input (during master mode) or slave output pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).
2.3.54 PS3 / TXD1 -- Port S I/O Pin 3
PS3 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial Communication Interface 1 (SCI1).
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2.3.55 PS2 / RXD1 -- Port S I/O Pin 2
PS2 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial Communication Interface 1 (SCI1).
2.3.56 PS1 / TXD0 -- Port S I/O Pin 1
PS1 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial Communication Interface 0 (SCI0).
2.3.57 PS0 / RXD0 -- Port S I/O Pin 0
PS0 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial Communication Interface 0 (SCI0).
2.3.58 PT[7:0] / IOC[7:0] -- Port T I/O Pins [7:0]
PT7-PT0 are general purpose input or output pins. They can be configured as input capture or output compare pins IOC7-IOC0 of the Enhanced Capture Timer (ECT).
2.4 Power Supply Pins
MC9S12A128 power and ground pins are described below. NOTE: All VSS pins must be connected together in the application.
2.4.1 VDDX, VSSX -- Power & Ground Pins for I/O Drivers
External power and ground for I/O drivers. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded.
2.4.2 VDDR, VSSR -- Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator
External power and ground for I/O drivers and input to the internal voltage regulator. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded.
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2.4.3 VDD1, VDD2, VSS1, VSS2 -- Core Power Pins
Power is supplied to the MCU through VDD and VSS. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. This 2.5V supply is derived from the internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is turned off, if VREGEN is tied to ground. NOTE: No load allowed except for bypass capacitors.
2.4.4 VDDA, VSSA -- Power Supply Pins for ATD and VREG
VDDA, VSSA are the power supply and ground input pins for the voltage regulator and the analog to digital converter. It also provides the reference for the internal voltage regulator. This allows the supply voltage to the ATD and the reference voltage to be bypassed independently.
2.4.5 VRH, VRL -- ATD Reference Voltage Input Pins
VRH and VRL are the reference voltage input pins for the analog to digital converter.
2.4.6 VDDPLL, VSSPLL -- Power Supply Pins for PLL
Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the supply voltage to the Oscillator and PLL to be bypassed independently. This 2.5V voltage is generated by the internal voltage regulator. NOTE: No load allowed except for bypass capacitors.
2.4.7 VREGEN -- On Chip Voltage Regulator Enable
Enables the internal 5V to 2.5V voltage regulator. If this pin is tied low, VDD1,2 and VDDPLL must be supplied externally.
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Table 2-2 MC9S12A128 Power and Ground Connection Summary
Mnemonic VDD1, 2 VSS1, 2 VDDR VSSR VDDX VSSX VDDA VSSA VRL VRH VDDPLL VSSPLL VREGEN Pin Number 112-pin QFP 13, 65 14, 66 41 40 107 106 83 86 85 84 43 45 97 Nominal Voltage 2.5 V 0V 5.0 V 0V 5.0 V 0V 5.0 V 0V 0V 5.0 V 2.5 V 0V 5V Description Internal power and ground generated by internal regulator External power and ground, supply to pin drivers and internal voltage regulator. External power and ground, supply to pin drivers. Operating voltage and ground for the analog-to-digital converters and the reference for the internal voltage regulator, allows the supply voltage to the A/D to be bypassed independently. Reference voltages for the analog-to-digital converter. Provides operating voltage and ground for the Phased-Locked Loop. This allows the supply voltage to the PLL to be bypassed independently. Internal power and ground generated by internal regulator. Internal Voltage Regulator enable/disable
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Section 3 System Clock Description
3.1 Overview
The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules. Figure 3-1 shows the clock connections from the CRG to all modules. Consult the HCS12 Clock and Reset Generator (CRG) Block Guide (Motorola document order number, S12CRGV3/D) for details on clock generation.
1/2
BDM
S12_CORE core clock
Flash RAM EEPROM EXTAL ECT ATD0, 1 CRG bus clock oscillator clock XTAL PWM SCI0, SCI1 SPI0, 1 IIC PIM
Figure 3-1 Clock Connections
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Section 4 Modes of Operation
4.1 Overview
Eight possible modes determine the operating configuration of the MC9S12A128. Each mode has an associated default memory map and external bus configuration. Three low power modes exist for the device.
4.2 Modes of Operation
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during reset (Table 4-1). The MODC, MODB, and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA pins are latched into these bits on the rising edge of the reset signal. Table 4-1 Mode Selection
MODC
0 0 0 0 1 1 1 1
MODB
0 0 1 1 0 0 1 1
MODA
0 1 0 1 0 1 0 1
Mode Description
Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all other modes but a serial command is required to make BDM active. Emulation Expanded Narrow, BDM allowed Special Test (Expanded Wide), BDM allowed Emulation Expanded Wide, BDM allowed Normal Single Chip, BDM allowed Normal Expanded Narrow, BDM allowed Peripheral; BDM allowed but bus operations would cause bus conflicts (must not be used) Normal Expanded Wide, BDM allowed
There are two basic types of operating modes: 1. Normal modes: Some registers and bits are protected against accidental changes. 2. Special modes: Allow greater access to protected control registers and bits for special purposes such as testing. A system development and debug feature, background debug mode (BDM), is available in all modes. In special single-chip mode, BDM is active immediately after reset. Some aspects of Port E are not mode dependent. Bit 1 of Port E is a general purpose input or the IRQ interrupt input. IRQ can be enabled by bits in the CPU's condition codes register but it is inhibited at reset so this pin is initially configured as a simple input with a pull-up. Bit 0 of Port E is a general purpose input or the XIRQ interrupt input. XIRQ can be enabled by bits in the CPU's condition codes register but it is inhibited at reset so this pin is initially configured as a simple input with a pull-up. The ESTR bit in the EBICTL register is set to one by reset in any user mode. This assures that the reset vector can be fetched
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even if it is located in an external slow memory device. The PE6/MODB/IPIPE1 and PE5/MODA/IPIPE0 pins act as high-impedance mode select inputs during reset. The following paragraphs discuss the default bus setup and describe which aspects of the bus can be changed after reset on a per mode basis.
4.2.1 Normal Operating Modes
These modes provide three operating configurations. Background debug is available in all three modes, but must first be enabled for some operations by means of a BDM background command, then activated. 4.2.1.1 Normal Single-Chip Mode There is no external expansion bus in this mode. All pins of Ports A, B and E are configured as general purpose I/O pins Port E bits 1 and 0 are available as general purpose input only pins with internal pull-ups enabled. All other pins of Port E are bidirectional I/O pins that are initially configured as high-impedance inputs with internal pull-ups enabled. Ports A and B are configured as high-impedance inputs with their internal pull-ups disabled. The pins associated with Port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1, IPIPE0, LSTRB, and R/W while the MCU is in single chip modes. In single chip modes, the associated control bits PIPOE, LSTRE, and RDWE are reset to zero. Writing the opposite state into them in single chip mode does not change the operation of the associated Port E pins. In normal single chip mode, the MODE register is writable one time. This allows a user program to change the bus mode to narrow or wide expanded mode and/or turn on visibility of internal accesses. Port E, bit 4 can be configured for a free-running E clock output by clearing NECLK=0. Typically the only use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock for use in the external application system. 4.2.1.2 Normal Expanded Wide Mode In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and Port E bit 4 is configured as the E clock output signal. These signals allow external memory and peripheral devices to be interfaced to the MCU. Port E pins other than PE4/ECLK are configured as general purpose I/O pins (initially high-impedance inputs with internal pull-up resistors enabled). Control bits PIPOE, NECLK, LSTRE, and RDWE in the PEAR register can be used to configure Port E pins to act as bus control outputs instead of general purpose I/O pins. It is possible to enable the pipe status signals on Port E bits 6 and 5 by setting the PIPOE bit in PEAR, but it would be unusual to do so in this mode. Development systems where pipe status signals are monitored would typically use the special variation of this mode. The Port E bit 2 pin can be reconfigured as the R/W bus control signal by writing "1" to the RDWE bit in PEAR. If the expanded system includes external devices that can be written, such as RAM, the RDWE bit
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would need to be set before any attempt to write to an external location. If there are no writable resources in the external system, PE2 can be left as a general purpose I/O pin. The Port E bit 3 pin can be reconfigured as the LSTRB bus control signal by writing "1" to the LSTRE bit in PEAR. The default condition of this pin is a general purpose input because the LSTRB function is not needed in all expanded wide applications. The Port E bit 4 pin is initially configured as ECLK output with stretch. The E clock output function depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and the ESTR bit in the EBICTL register. The E clock is available for use in external select decode logic or as a constant speed clock for use in the external application system. 4.2.1.3 Normal Expanded Narrow Mode This mode is used for lower cost production systems that use 8-bit wide external EPROMs or RAMs. Such systems take extra bus cycles to access 16-bit locations but this may be preferred over the extra cost of additional external memory devices. Ports A and B are configured as a 16-bit address bus and Port A is multiplexed with data. Internal visibility is not available in this mode because the internal cycles would need to be split into two 8-bit cycles. Since the PEAR register can only be written one time in this mode, use care to set all bits to the desired states during the single allowed write. The PE3/LSTRB pin is always a general purpose I/O pin in normal expanded narrow mode. Although it is possible to write the LSTRE bit in PEAR to "1" in this mode, the state of LSTRE is overridden and Port E bit 3 cannot be reconfigured as the LSTRB output. It is possible to enable the pipe status signals on Port E bits 6 and 5 by setting the PIPOE bit in PEAR, but it would be unusual to do so in this mode. LSTRB would also be needed to fully understand system activity. Development systems where pipe status signals are monitored would typically use special expanded wide mode or occasionally special expanded narrow mode. The PE4/ECLK pin is initially configured as ECLK output with stretch. The E clock output function depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and the ESTR bit in the EBICTL register. In normal expanded narrow mode, the E clock is available for use in external select decode logic or as a constant speed clock for use in the external application system. The PE2/R/W pin is initially configured as a general purpose input with a pull-up but this pin can be reconfigured as the R/W bus control signal by writing "1" to the RDWE bit in PEAR. If the expanded narrow system includes external devices that can be written such as RAM, the RDWE bit would need to be set before any attempt to write to an external location. If there are no writable resources in the external system, PE2 can be left as a general purpose I/O pin. 4.2.1.4 Internal Visibility Internal visibility is available when the MCU is operating in expanded wide modes or emulation narrow mode. It is not available in single-chip, peripheral or normal expanded narrow modes. Internal visibility is enabled by setting the IVIS bit in the MODE register.
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If an internal access is made while E, R/W, and LSTRB are configured as bus control outputs and internal visibility is off (IVIS=0), E will remain low for the cycle, R/W will remain high, and address, data and the LSTRB pins will remain at their previous state. When internal visibility is enabled (IVIS=1), certain internal cycles will be blocked from going external. During cycles when the BDM is selected, R/W will remain high, data will maintain its previous state, and address and LSTRB pins will be updated with the internal value. During CPU no access cycles when the BDM is not driving, R/W will remain high, and address, data and the LSTRB pins will remain at their previous state. 4.2.1.5 Emulation Expanded Wide Mode In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and Port E provides bus control and status signals. These signals allow external memory and peripheral devices to be interfaced to the MCU. These signals can also be used by a logic analyzer to monitor the progress of application programs. The bus control related pins in Port E (PE7/NOACC, PE6/MODB/IPIPE1, PE5/MODA/IPIPE0, PE4/ECLK, PE3/LSTRB/TAGLO, and PE2/R/W) are all configured to serve their bus control output functions rather than general purpose I/O. Notice that writes to the bus control enable bits in the PEAR register in emulation mode are restricted. 4.2.1.6 Emulation Expanded Narrow Mode Expanded narrow modes are intended to allow connection of single 8-bit external memory devices for lower cost systems that do not need the performance of a full 16-bit external data bus. Accesses to internal resources that have been mapped external (i.e. PORTA, PORTB, DDRA, DDRB, PORTE, DDRE, PEAR, PUCR, RDRIV) will be accessed with a 16-bit data bus on Ports A and B. Accesses of 16-bit external words to addresses which are normally mapped external will be broken into two separate 8-bit accesses using Port A as an 8-bit data bus. Internal operations continue to use full 16-bit data paths. They are only visible externally as 16-bit information if IVIS=1. Ports A and B are configured as multiplexed address and data output ports. During external accesses, address A15, data D15 and D7 are associated with PA7, address A0 is associated with PB0 and data D8 and D0 are associated with PA0. During internal visible accesses and accesses to internal resources that have been mapped external, address A15 and data D15 is associated with PA7 and address A0 and data D0 is associated with PB0. The bus control related pins in Port E (PE7/NOACC, PE6/MODB/IPIPE1, PE5/MODA/IPIPE0, PE4/ECLK, PE3/LSTRB/TAGLO, and PE2/R/W) are all configured to serve their bus control output functions rather than general purpose I/O. Notice that writes to the bus control enable bits in the PEAR register in emulation mode are restricted. The main difference between special modes and normal modes is that some of the bus control and system control signals cannot be written in emulation modes.
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4.2.2 Special Operating Modes
There are two special operating modes that correspond to normal operating modes. These operating modes are commonly used in factory testing and system development. 4.2.2.1 Special Single-Chip Mode When the MCU is reset in this mode, the background debug mode is enabled and active. The MCU does not fetch the reset vector and execute application code as it would in other modes. Instead the active background mode is in control of CPU execution and BDM firmware is waiting for additional serial commands through the BKGD pin. When a serial command instructs the MCU to return to normal execution, the system will be configured as described below unless the reset states of internal control registers have been changed through background commands after the MCU was reset. There is no external expansion bus after reset in this mode. Ports A and B are initially simple bidirectional I/O pins that are configured as high-impedance inputs with internal pull-ups disabled; however, writing to the mode select bits in the MODE register (which is allowed in special modes) can change this after reset. All of the Port E pins (except PE4/ECLK) are initially configured as general purpose high-impedance inputs with pull-ups enabled. PE4/ECLK is configured as the E clock output in this mode. The pins associated with Port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1, IPIPE0, LSTRB, and R/W while the MCU is in single chip modes. In single chip modes, the associated control bits PIPOE, LSTRE and RDWE are reset to zero. Writing the opposite value into these bits in single chip mode does not change the operation of the associated Port E pins. Port E, bit 4 can be configured for a free-running E clock output by clearing NECLK=0. Typically the only use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock for use in the external application system. 4.2.2.2 Special Test Mode In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and Port E provides bus control and status signals. In special test mode, the write protection of many control bits is lifted so that they can be thoroughly tested without needing to go through reset.
4.2.3 Test Operating Mode
There is a test operating mode in which an external master, such as an I.C. tester, can control the on-chip peripherals. 4.2.3.1 Peripheral Mode This mode is intended for Motorola factory testing of the MCU. In this mode, the CPU is inactive and an external (tester) bus master drives address, data and bus control signals in through Ports A, B and E. In effect, the whole MCU acts as if it was a peripheral under control of an external CPU. This allows faster testing of on-chip memory and peripherals than previous testing methods. Since the mode control register is not accessible in peripheral mode, the only way to change to another mode is to reset the MCU into a different mode. Background debugging should not be used while the MCU is in special peripheral mode
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as internal bus conflicts between BDM and the external master can cause improper operation of both functions.
4.3 Security
The device will make available a security feature preventing the unauthorized read and write of the memory contents. This feature allows: * * * * Protection of the contents of FLASH, Protection of the contents of EEPROM, Operation in single-chip mode, Operation from external memory with internal FLASH and EEPROM disabled.
The user must be reminded that part of the security must lie with the user's code. An extreme example would be user's code that dumps the contents of the internal program. This code would defeat the purpose of security. At the same time the user may also wish to put a back door in the user's program. An example of this is the user downloads a key through the SCI which allows access to a programming routine that updates parameters stored in EEPROM.
4.3.1 Securing the Microcontroller
Once the user has programmed the FLASH and EEPROM (if desired), the part can be secured by programming the security bits located in the FLASH module. These non-volatile bits will keep the part secured through resetting the part and through powering down the part. The security byte resides in a portion of the Flash array. Check the HCS12 128K Flash Block Guide (Motorola document order number, S12FTS128KV1/D) for more details on the security configuration.
4.3.2 Operation of the Secured Microcontroller
4.3.2.1 Normal Single Chip Mode This will be the most common usage of the secured part. Everything will appear the same as if the part was not secured with the exception of BDM operation. The BDM operation will be blocked. 4.3.2.2 Executing from External Memory The user may wish to execute from external space with a secured microcontroller. This is accomplished by resetting directly into expanded mode. The internal FLASH and EEPROM will be disabled. BDM operations will be blocked.
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4.3.3 Unsecuring the Microcontroller
In order to unsecure the microcontroller, the internal FLASH and EEPROM must be erased. This can be done through an external program in expanded mode. Once the user has erased the FLASH and EEPROM, the part can be reset into special single chip mode. This invokes a program that verifies the erasure of the internal FLASH and EEPROM. Once this program completes, the user can erase and program the FLASH security bits to the unsecured state. This is generally done through the BDM, but the user could also change to expanded mode (by writing the mode bits through the BDM) and jumping to an external program (again through BDM commands). Note that if the part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be secured again.
4.4 Low Power Modes
Consult the respective Block Guide for information on the module behavior in Stop, Pseudo Stop, and Wait Mode.
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Section 5 Resets and Interrupts
5.1 Overview
Consult the Exception Processing section of the HCS12 Core User Guide (Motorola document order number HCS12COREUG/D) for information on resets and interrupts.
5.2 Vectors
5.2.1 Vector Table
Table 5-1 lists interrupt sources and vectors in default order of priority. Table 5-1 Interrupt Vector Locations
Vector Address
$FFFE, $FFFF $FFFC, $FFFD $FFFA, $FFFB $FFF8, $FFF9 $FFF6, $FFF7 $FFF4, $FFF5 $FFF2, $FFF3 $FFF0, $FFF1 $FFEE, $FFEF $FFEC, $FFED $FFEA, $FFEB $FFE8, $FFE9 $FFE6, $FFE7 $FFE4, $FFE5 $FFE2, $FFE3 $FFE0, $FFE1 $FFDE, $FFDF $FFDC, $FFDD $FFDA, $FFDB $FFD8, $FFD9 $FFD6, $FFD7 $FFD4, $FFD5 $FFD2, $FFD3 $FFD0, $FFD1 $FFCE, $FFCF $FFCC, $FFCD $FFCA, $FFCB
Interrupt Source
Reset Clock Monitor fail reset COP failure reset Unimplemented instruction trap SWI XIRQ IRQ Real Time Interrupt Enhanced Capture Timer channel 0 Enhanced Capture Timer channel 1 Enhanced Capture Timer channel 2 Enhanced Capture Timer channel 3 Enhanced Capture Timer channel 4 Enhanced Capture Timer channel 5 Enhanced Capture Timer channel 6 Enhanced Capture Timer channel 7 Enhanced Capture Timer overflow Pulse accumulator A overflow Pulse accumulator input edge SPI0 SCI0 SCI1 ATD0 ATD1 Port J Port H Modulus Down Counter underflow
CCR Mask
None None None None None X-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit
Local Enable
None PLLCTL (CME, SCME) COP rate select None None None IRQCR (IRQEN) CRGINT (RTIE) TIE (C0I) TIE (C1I) TIE (C2I) TIE (C3I) TIE (C4I) TIE (C5I) TIE (C6I) TIE (C7I) TSRC2 (TOF) PACTL (PAOVI) PACTL (PAI) SP0CR1 (SPIE, SPTIE) SC0CR2 (TIE, TCIE, RIE, ILIE) SC1CR2 (TIE, TCIE, RIE, ILIE) ATD0CTL2 (ASCIE) ATD1CTL2 (ASCIE) PTJIF (PTJIE) PTHIF(PTHIE) MCCTL(MCZI)
HPRIO Value to Elevate
- - - - - - $F2 $F0 $EE $EC $EA $E8 $E6 $E4 $E2 $E0 $DE $DC $DA $D8 $D6 $D4 $D2 $D0 $CE $CC $CA
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$FFC8, $FFC9 $FFC6, $FFC7 $FFC4, $FFC5 $FFC2, $FFC3 $FFC0, $FFC1 $FFBE, $FFBF $FFBC, $FFBD $FFBA, $FFBB $FFB8, $FFB9 $FF90 to $FFB7 $FF8E, $FF8F $FF8C, $FF8D $FF80 to $FF8B Port P Interrupt PWM Emergency Shutdown EEPROM FLASH IIC Bus SPI1 Pulse Accumulator B Overflow CRG PLL lock CRG Self Clock Mode I-Bit I-Bit I-Bit Reserved I-Bit I-Bit Reserved I-Bit I-Bit Reserved I-Bit I-Bit Reserved PTPIF (PTPIE) PWMSDN (PWMIE) $8E $8C EECTL(CCIE, CBEIE) FCTL(CCIE, CBEIE) $BA $B8 IBCR (IBIE) SP1CR1 (SPIE, SPTIE) $C0 $BE PBCTL(PBOVI) CRGINT(LOCKIE) CRGINT (SCMIE) $C8 $C6 $C4
5.3 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the respective module Block User Guides for register reset states.
5.3.1 I/O Pins
Refer to the HCS12 Core User Guide (Motorola document order number HCS12COREUG/D) for mode dependent pin configuration of port A, B, E and K out of reset. Refer to the MC9S12A128 Port Integration Module (PIM) Block Guide (Motorola document order number, S12A128PIMV1/D) for reset configurations of all peripheral module ports. NOTE: For devices assembled in 80-pin QFP packages all non-bonded out pins should be configured as outputs after reset in order to avoid current drawn from floating inputs. Refer to Table 2-1 Signal Properties for affected pins.
5.3.2 Memory
Refer to Table 1-1 Device Memory Map for locations of the memories depending on the operating mode after reset. The RAM array is not automatically initialized out of reset.
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Section 6 HCS12 Core Block Description
Consult the HCS12 Core User Guide (Motorola document order number HCS12COREUG/D) for information about the HCS12 core modules, i.e. central processing unit (CPU), interrupt module (INT), module mapping control module (MMC), multiplexed external bus interface (MEBI), breakpoint module (BKP) and background debug mode module (BDM).
Section 7 Clock and Reset Generator (CRG) Block Description
Consult the HCS12 Clock and Reset Generator (CRG) Block Guide (Motorola document order number, S12CRGV3/D) for information about the Clock and Reset Generator module.
7.1 Device-Specific Information
7.1.1 XCLKS
The XCLKS input signal is active low (see 2.3.13 PE7 / NOACC / XCLKS -- Port E I/O Pin 7). Refer to Figure 2-3. Pierce Oscillator Connections (XCLKS=1) of the HCS12 Clock and Reset Generator (CRG) Block Guide (Motorola document order number, S12CRGV3/D).
Section 8 Enhanced Capture Timer (ECT) Block Description
Consult the HCS12 16-Bit, 8-Channel Enhanced Capture Timer (ECT) Block Guide (Motorola document order number, S12ECT16B8CV1/D) for information about the Enhanced Capture Timer module.
Section 9 Analog to Digital Converter (ATD) Block Description
There are two Analog to Digital Converters (ATD1 and ATD0) implemented on the MC9S12A128. Consult the HCS12 10-Bit, 8-Channel Analog-to-Digital Converter (ATD) Block Guide (Motorola document order number, S12ATD10B8CV2/D) for information about each Analog to Digital Converter module.
Section 10 Inter-IC Bus (IIC) Block Description
Consult the HCS12 Inter-Integrated Circuit (IIC) Block Guide (Motorola document order number, S12IICV2/D) for information about the Inter-IC Bus module.
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Section 11 Serial Communications Interface (SCI) Block Description
There are two Serial Communications Interfaces (SCI1 and SCI0) implemented on the MC9S12A128 device. Consult the HCS12 Serial Communications Interface (SCI) Block Guide (Motorola document order number, S12SCIV2/D) for information about each Serial Communications Interface module.
Section 12 Serial Peripheral Interface (SPI) Block Description
There are two Serial Peripheral Interfaces (SPI1 and SPI0) implemented on MC9S12A128. Consult the HCS12 Serial Peripheral Interface (SPI) Block Guide (Motorola document order number, S12SPIV2/D) for information about each Serial Peripheral Interface module.
Section 13 Pulse Width Modulator (PWM) Block Description
Consult the HCS12 8-Bit, 8-Channel Pulse Width Modulator (PWM) Block Guide (Motorola document order number, S12PWM8B8CV1/D) for information about the Pulse Width Modulator module.
Section 14 Flash EEPROM 128K Block Description
Consult the HCS12 128K FLASH Block Guide (Motorola document order number, S12FTS128KV1/D) for information about the flash module.
Section 15 EEPROM 2K Block Description
Consult the HCS12 2K EEPROM Block Guide (Motorola document order number, S12EETS2KV1/D) for information about the EEPROM module.
Section 16 RAM Block Description
This module supports single-cycle misaligned word accesses.
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Section 17 Port Integration Module (PIM) Block Description
Consult the MC9S12A128 Port Integration Module (PIM) Block Guide (Motorola document order number, S12A128PIMV1/D) for information about the Port Integration Module.
Section 18 Voltage Regulator (VREG) Block Description
Consult the HCS12 Voltage Regulator Block Guide (Motorola document order number, S12VREGV1/D) for information about the dual output linear voltage regulator.
Component C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 R1 Q1
Purpose VDD1 filter cap VDD2 filter cap VDDA filter cap VDDR filter cap VDDPLL filter cap VDDX filter cap OSC load cap OSC load cap PLL loop filter cap PLL loop filter cap
Type ceramic X7R ceramic X7R ceramic X7R X7R/tantalum ceramic X7R X7R/tantalum
Value 100 .. 220nF 100 .. 220nF 100nF >=100nF 100nF >=100nF
See A.5.3 Phase Locked Loop DC cutoff cap PLL loop filter res Quartz
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The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the MCU itself. The following rules must be observed: * * * * * * * Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins (C1 - C6). Central point of the ground star should be the VSSR pin. Use low ohmic low inductance connections between VSS1, VSS2 and VSSR. VSSPLL must be directly connected to VSSR. Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C7, C8, C11 and Q1 as small as possible. Do not place other signals or supplies underneath area occupied by C7, C8, C10 and Q1 and the connection area to the MCU. Central power input should be fed in at the VDDA/VSSA pins.
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Figure 18-1 Recommended PCB Layout 112 LQFP
VREGEN
VDDX
C6
VSSX
VSSA
C3
VDDA
VDD1 C1 VSS1 VSS2 C2 VDD2
VSSR
C4 C5
VDDR
C11
C8
Q1
C7
C9
R1
C10
VSSPLL VDDPLL
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Figure 18-2 Recommended PCB Layout for 80 QFP
VDDX
C6
VREGEN
VSSX
VSSA
C3
VDDA
VDD1
C1
VSS2 C2 VSS1 VDD2
VSSR
C4 C5
VDDR
C11
C8
C7
Q1
C10
R1
C9
VSSPLL VDDPLL
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Appendix A Electrical Characteristics
A.1 General
NOTE: The electrical characteristics given in this section are preliminary and should be used as a guide only. Values cannot be guaranteed by Motorola and are subject to change without notice.
This supplement contains the most accurate electrical information for the MC9S12A128 microcontroller available at the time of publication. The information should be considered PRELIMINARY and is subject to change. This introduction is intended to give an overview on several common topics like power supply, current injection etc.
A.1.1 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate. NOTE: P: Those parameters are guaranteed during production testing on each individual device. C: Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T: Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D: Those parameters are derived mainly from simulations. This classification is shown in the column labeled "C" in the parameter tables where appropriate.
A.1.2 Power Supply
The MC9S12A128 utilizes several pins to supply power to the I/O ports, A/D converter, oscillator and PLL as well as the digital core. The VDDA, VSSA pair supplies the A/D converter and the resistor ladder of the internal voltage regulator.
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The VDDX, VSSX, VDDR and VSSR pairs supply the I/O pins, VDDR supplies also the internal voltage regulator. VDD1, VSS1, VDD2 and VSS2 are the supply pins for the digital logic, VDDPLL, VSSPLL supply the oscillator and the PLL. VSS1 and VSS2 are internally connected by metal. VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD protection. NOTE: In the following context VDD5 is used for either VDDA, VDDR and VDDX; VSS5 is used for either VSSA, VSSR and VSSX unless otherwise noted. IDD5 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR pins. VDD is used for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and VSSPLL. IDD is used for the sum of the currents flowing into VDD1 and VDD2.
A.1.3 Pins
There are four groups of functional pins. A.1.3.1 5V I/O pins Those I/O pins have a nominal level of 5V. This class of pins is comprised of all port I/O pins, the analog inputs, BKGD and the RESET pins.The internal structure of all those pins is identical, however some of the functionality may be disabled. E.g. for the analog inputs the output drivers, pull-up and pull-down resistors are disabled permanently. A.1.3.2 Analog Reference This group is made up by the VRH and VRL pins. A.1.3.3 Oscillator The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied by VDDPLL. A.1.3.4 TEST This pin is used for production testing only. A.1.3.5 VREGEN This pin is used to enable the on chip voltage regulator.
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A.1.4 Current Injection
Power supply must maintain regulation within operating VDD5 or VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD5) is greater than IDD5, the injection current may flow out of VDD5 and could result in external power supply going out of regulation. Ensure external VDD5 load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption.
A.1.5 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5). Table A-1 Absolute Maximum Ratings(1)
Num
1 2 3 4 5 6 7 8 9 10 11 12 13
Rating
I/O, Regulator and Analog Supply Voltage Digital Logic Supply Voltage PLL Supply Voltage
2 (2)
Symbol
VDD5 VDD VDDPLL VDDX VSSX VIN VRH, VRL VILV VTEST I I
D
Min
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -25 -25 -0.25 -65
Max
6.0 3.0 3.0 0.3 0.3 6.0 6.0 3.0 10.0 +25 +25 0 155
Unit
V V V V V V V V V mA mA mA C
Voltage difference V DDX to VDDR and VDDA Voltage difference V SSX to VSSR and VSSA Digital I/O Input Voltage Analog Reference XFC, EXTAL, XTAL inputs TEST input Instantaneous Maximum Current Single pin limit for all digital I/O pins (3) Instantaneous Maximum Current Single pin limit for XFC, EXTAL, XTAL(4) Instantaneous Maximum Current Single pin limit for TEST (5) Storage Temperature Range
DL
IDT T
stg
NOTES: 1. Beyond absolute maximum ratings device might be damaged. 2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when the device is powered from an external source. 3. All digital I/O pins are internally clamped to V SSX and VDDX, VSSR and V DDR or VSSA and VDDA. 4. Those pins are internally clamped to VSSPLL and VDDPLL. 5. This pin is clamped low to VSSPLL, but not clamped high. This pin must be tied low in applications.
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A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table A-2 ESD and Latch-up Test Conditions
Model
Series Resistance Storage Capacitance Human Body Number of Pulse per pin positive negative Series Resistance Storage Capacitance Machine Number of Pulse per pin positive negative Minimum input voltage limit Latch-up Maximum input voltage limit -- 7.5 V
Description
Symbol
R1 C -- -- R1 C -- -- --
Value
1500 100 3 3 0 200 3 3 -2.5
Unit
Ohm pF
Ohm pF
V
Table A-3 ESD and Latch-Up Protection Characteristics
Num C
1 2 3 4
Rating
Symbol
VHBM VMM VCDM ILAT
Min
2000 200 500 +100 -100 +200 -200
Max
-- -- -- -- -- -- --
Unit
V V V mA
C Human Body Model (HBM) C Machine Model (MM) C Charge Device Model (CDM) Latch-up Current at TA = 125C C positive negative Latch-up Current at TA = 27C C positive negative
5
ILAT
mA
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A.1.7 Operating Conditions
This chapter describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. NOTE: Please refer to the temperature rating of the device (C) with regards to the ambient temperature TA and the junction temperature TJ. For power dissipation calculations refer to A.1.8 Power Dissipation and Thermal Characteristics. Table A-4 Operating Conditions
Rating
I/O, Regulator and Analog Supply Voltage Digital Logic Supply Voltage(1) PLL Supply Voltage(2) Voltage Difference VDDX to VDDR and V DDA Voltage Difference VSSX to VSSR and VSSA Oscillator Bus Frequency MC9S12A128C Operating Junction Temperature Range Operating Ambient Temperature Range (2) TJ T
A
Symbol
VDD5 VDD VDDPLL VDDX VSSX fosc fbus
Min
4.5 2.35 2.25 -0.1 -0.1 0.5 0.5
Typ
5 2.5 2.5 0 0 -- --
Max
5.25 2.75 2.75 0.1 0.1 16 25
Unit
V V V V V MHz MHz
-40 -40
-- 27
100 85
C C
NOTES: 1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when this regulator is disabled and the device is powered from an external source. 2. Please refer to A.1.8 Power Dissipation and Thermal Characteristics for more details about the relation between ambient temperature TA and device junction temperature TJ.
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A.1.8 Power Dissipation and Thermal Characteristics
Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in C can be obtained from:
T T T J A D = Junction Temperature, [C ] = Ambient Temperature, [C ] = Total Chip Power Dissipation, [W] = Package Thermal Resistance, [C/W] J = T + (P * ) A D JA
P
JA
The total power dissipation can be calculated from:
P P INT D =P INT +P IO
= Chip Internal Power Dissipation, [W]
Two cases with internal voltage regulator enabled and disabled must be considered: 1. Internal Voltage Regulator disabled
P INT =I DD V DD +I = DDPLL V DDPLL +I 2 DDA V DDA
P
IO
RDSON IIOi
i
PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR. For RDSON is valid:
R V OL = ----------- ;for outputs driven low DSON I OL
respectively
R V -V DD5 OH = ----------------------------------- ;for outputs driven high DSON I OH
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MC9S12A128 Device Guide -- V01.01
2. Internal voltage regulator enabled
P INT =I DDR V DDR +I DDA V DDA
IDDR is the current shown in Table A-7 and not the overall current flowing into VDDR, which additionally contains the current flowing into the external loads with output high.
P IO =
RDSON IIOi
i
2
PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR.
Table A-5 Thermal Package Characteristics(1)
Num C
1 2 3 4
Rating
Symbol
JA JA JA JA
Min
-- -- -- --
Typ
-- -- -- --
Max
54 41 51 41
Unit
o
T Thermal Resistance LQFP112, single sided PCB(2) T Thermal Resistance LQFP112, double sided PCB with 2 internal planes(3)
C/W C/W C/W C/W
o
T Thermal Resistance LQFP 80, single sided PCB T Thermal Resistance LQFP 80, double sided PCB with 2 internal planes
o o
NOTES: 1. The values for thermal resistance are achieved by package simulations 2. PC Board according to EIA/JEDEC Standard 51-2 3. PC Board according to EIA/JEDEC Standard 51-7
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A.1.9 I/O Characteristics
This section describes the characteristics of all 5V I/O pins. All parameters are not always applicable, e.g. not all pins feature pull up/down resistances. Table A-6 5V I/O Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 P Input High Voltage T Input High Voltage 2 P Input Low Voltage T Input Low Voltage 3 C Input Hysteresis
Rating
Symbol
V
IH
Min
0.65*VDD5 -- -- VSS5 - 0.3 --
Typ
-- -- -- -- 250
Max
-- VDD5 + 0.3 0.35*VDD5 -- --
Unit
V V V V mV A
VIH VIL VIL V
HYS
Input Leakage Current (pins in high impedance input 4 P mode)(1) Vin = VDD5 or VSS5 Output High Voltage (pins in output mode) P Partial Drive IOH = -2.0mA Full Drive IOH = -10.0mA Output Low Voltage (pins in output mode) P Partial Drive IOL = +2.0mA Full Drive IOL = +10.0mA Internal Pull Up Device Current, P tested at V Max.
IL
I
in
-2.5
--
2.5
5
V
OH
VDD5 - 0.8
--
--
V
6
VOL
--
--
0.8
V
7
IPUL IPUH IPDH IPDL Cin IICS IICP tPULSE tPULSE
--
--
-130
A A A A pF mA s s
8
Internal Pull Up Device Current, P tested at V Min. IH Internal Pull Down Device Current, P tested at V Min.
IH
-10
--
--
9
--
--
130
10 11 12 13 14
Internal Pull Down Device Current, P tested at V Max.
IL
10 -- -2.5 -25 -- 10
-- 6 -- -- --
-- -- 2.5 25 3 --
D Input Capacitance Injection current(2) T Single Pin limit Total Device Limit. Sum of all injected currents P Port H, J, P Interrupt Input Pulse filtered(3) P Port H, J, P Interrupt Input Pulse passed
(3)
NOTES: 1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8C to 12C in the temperature range from 50C to 125C. 2. Refer to A.1.4 Current Injection, for more details 3. Parameter only applies in STOP or Pseudo STOP mode.
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A.1.10 Supply Currents
This section describes the current consumption characteristics of the device as well as the conditions for the measurements. A.1.10.1 Measurement Conditions All measurements are without output loads. Unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator in Colpitts mode. Production testing is performed using a square wave signal at the EXTAL input. A.1.10.2 Additional Remarks In expanded modes the currents flowing in the system are highly dependent on the load at the address, data and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be given. A very good estimate is to take the single chip currents and add the currents due to the external loads. Table A-7 Supply Current Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 P
Rating
Run supply currents Single Chip, Internal regulator enabled Wait Supply current All modules enabled, PLL on only RTI enabled(1) Pseudo Stop Current (RTI and COP disabled) (1), (2) -40C 27C 70C 85C "C" Temp Option 100C 105C Pseudo Stop Current (RTI and COP enabled)(1) ,(2) -40C 27C 70C 85C 105C Stop Current(2)
Symbol
IDD5
Min
--
Typ
--
Max
65
Unit
mA
2
P P C P C C P C
IDDW
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- 370 400 450 550 600 650
40 5
mA
500 A 1600
3
IDDPS
4
C C C C C
IDDPS
570 600 650 750 850
-- -- -- -- -- --
A
5
C P C C P C
-40C 27C 70C 85C "C" Temp Option 100C 105C
IDDS
12 25 100 130 160 200
100 A 1200
NOTES: 1. PLL off 2. At those low power dissipation levels TJ = TA can be assumed
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A.2 ATD Characteristics
This section describes the characteristics of the analog to digital converter.
A.2.1 ATD Operating Characteristics
The Table A-8 shows conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: VSSA VRL VIN VRH VDDA. This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped. Table A-8 ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Reference Potential 1 D
Rating
Low High
Symbol VRL VRH VRH-VRL fATDCLK
Min VSSA VDDA/2 4.50 0.5 14 7 12 6 -- -- --
Typ -- -- 5.00 -- -- --
Max VDDA/2 VDDA 5.25 2.0 28 14 26 13
Unit V V V MHz Cycles s Cycles s s mA mA
2 3
C Differential Reference Voltage(1) D ATD Clock Frequency ATD 10-Bit Conversion Period
4
D
Clock Cycles(2) NCONV10 Conv, Time at 2.0MHz ATD Clock fATDCLK TCONV10 ATD 8-Bit Conversion Period Clock Cycles(2) Conv, Time at 2.0MHz ATD Clock fATDCLK
5
D
NCONV8 TCONV8 tSR IREF IREF
6 7 8
D Stop Recovery Time (VDDA=5.0 Volts) P Reference Supply current (Both ATD blocks on) P Reference Supply current (Only one ATD block on)
-- -- --
20 0.750 0.375
NOTES: 1. Full accuracy is not guaranteed when differential voltage is less than 4.50V 2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks.
A.2.2 Factors Influencing accuracy
Three factors -- source resistance, source capacitance and current injection -- have an influence on the accuracy of the ATD. A.2.2.1 Source Resistance Due to the input pin leakage current as specified in Table A-6 in conjunction with the source resistance there will be a voltage drop from the signal source to the ATD input. The maximum source resistance RS
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specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance is allowed. A.2.2.2 Source Capacitance When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input voltage 1LSB, then the external filter capacitor, Cf 1024 * (CINS- CINN). A.2.2.3 Current Injection There are two cases to consider. 1. A current is injected into the channel being converted. The channel being stressed has conversion values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less than VRL unless the current is higher than specified as disruptive condition. 2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy of the conversion depending on the source resistance. The additional input voltage error on the converted channel can be calculated as VERR = K * RS * IINJ, with IINJ being the sum of the currents injected into the two pins adjacent to the converted channel. Table A-9 ATD Electrical Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1
Rating
Symbol
RS CINN CINS INA Kp Kn
Min
--
Typ
--
Max
1
Unit
K
C Max input Source Resistance Total Input Capacitance T Non Sampling Sampling C Disruptive Analog Input Current C Coupling Ratio positive current injection C Coupling Ratio negative current injection
2
-- -- -2.5 -- --
-- -- -- -- --
10 22 2.5 10-4 10-2
pF
3 4 5
mA A/A A/A
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A.2.3 ATD Accuracy
Table A-10 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. Table A-10 ATD Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted VREF = VRH - VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV fATDCLK = 2.0MHz
Num C
1 2 3 4 5 6 7 8 P 10-Bit Resolution
Rating
Symbol
LSB DNL INL AE LSB DNL INL AE
Min
-- -1 -2.5 -3 -- -0.5 -1.0 -1.5
Typ
5
Max
-- 1
Unit
mV Counts Counts Counts mV Counts Counts Counts
P 10-Bit Differential Nonlinearity P 10-Bit Integral Nonlinearity P 10-Bit Absolute Error(1) P 8-Bit Resolution P 8-Bit Differential Nonlinearity P 8-Bit Integral Nonlinearity P 8-Bit Absolute Error(1)
1.5 2.0 20 -- 0.5 1.0
2.5 3 -- 0.5 1.0 1.5
NOTES: 1. These values include the quantization error which is inherently 1/2 count for any A/D converter.
For the following definitions see also Figure A-1. Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.
V -V i i-1 DNL ( i ) = ------------------------- - 1 1LSB
The Integral Non-Linearity (INL) is defined as the sum of all DNLs:
n INL ( n ) =
i=1
V -V n 0 DNL ( i ) = -------------------- - n 1LSB
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MC9S12A128 Device Guide -- V01.01
DNL
LSB Vi-1
$3FF $3FE $3FD $3FC $3FB $3FA $3F9 $3F8 $3F7 $3F6 $3F5
10-Bit Absolute Error Boundary Vi 8-Bit Absolute Error Boundary
$FF
$FE
10-Bit Resolution
$3F4 $3F3
$FD
9 8 7 6 5 4 3 2 1 0 5 10 15 20 25 30 35 40 45
Ideal Transfer Curve
2
10-Bit Transfer Curve
1
8-Bit Transfer Curve
5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120
Vin mV
Figure A-1 ATD Accuracy Definitions NOTE: Figure A-1 shows only definitions, for specification values refer to Table A-10.
8-Bit Resolution
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A.3 NVM, Flash, and EEPROM
NOTE: Unless otherwise noted the abbreviation NVM (Non Volatile Memory) is used for both Flash and EEPROM.
A.3.1 NVM Timing
The time base for all NVM program or erase operations is derived from the oscillator. A minimum oscillator frequency fNVMOSC is required for performing program or erase operations. The NVM modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at a lower frequency a full program or erase transition is not assured. The Flash and EEPROM program and erase operations are timed using a clock derived from the oscillator using the FCLKDIV and ECLKDIV registers respectively. The frequency of this clock must be set within the limits specified as fNVMOP. The minimum program and erase times shown in Table A-11 are calculated for maximum fNVMOP and maximum fbus. The maximum times are calculated for minimum fNVMOP and a fbus of 2MHz.
A.3.1.1 Single Word Programming The programming time for single word programming is dependant on the bus frequency as a well as on the frequency fNVMOP and can be calculated according to the following formula.
t swpgm 1 1 = 9 ------------------------ + 25 ----------f f bus NVMOP
A.3.1.2 Burst Programming This applies only to the Flash where up to 32 words in a row can be programmed consecutively using burst programming by keeping the command pipeline filled. The time to program a consecutive word can be calculated as:
t bwpgm 1 1 = 4 ------------------------ + 9 ----------f f bus NVMOP
The time to program a whole row is:
t brpgm =t swpgm + 31 t bwpgm
Burst programming is more than 2 times faster than single word programming.
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A.3.1.3 Sector Erase Erasing a 512 byte Flash sector or a 4 byte EEPROM sector takes:
t era 1 4000 -----------------------f NVMOP
The setup time can be ignored for this operation. A.3.1.4 Mass Erase Erasing a NVM block takes:
t mass 1 20000 -----------------------f NVMOP
The setup time can be ignored for this operation. A.3.1.5 Blank Check The time it takes to perform a blank check on the Flash or EEPROM is dependant on the location of the first non-blank word starting at relative address zero. It takes one bus cycle per word to verify plus a setup of the command.
t check location t cyc + 10 t cyc
Table A-11 NVM Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 2 3 4 5 6 7 8 9 10
Rating
Symbol
fNVMOSC fNVMBUS fNVMOP tswpgm tbwpgm tbrpgm tera tmass tcheck tcheck
Min
0.5 1 150 46(2) 20.4(2) 678.4(2) 20(5) 100
(5)
Typ
-- -- -- -- -- -- -- -- -- --
Max
50
(1)
Unit
MHz MHz
D External Oscillator Clock D Bus frequency for Programming or Erase Operations D Operating Frequency P Single Word Programming Time D Flash Burst Programming consecutive word (4) D Flash Burst Programming Time for 32 Words 4 P Sector Erase Time P Mass Erase Time D Blank Check Time Flash per block D Blank Check Time EEPROM per block
200 74.5(3) 31(3) 1035.5(3) 26.7(3) 133
(3)
kHz s s s ms ms tcyc tcyc
11(6) 11(6)
32,778(7) 2058(7)
NOTES: 1. Restrictions for oscillator in crystal mode apply! 2. Minimum Programming times are achieved under maximum NVM operating frequency fNVMOP and maximum bus frequency fbus. 3. Maximum Erase and Programming times are achieved under particular combinations of fNVMOP and bus frequency fbus. Refer to formulae in A.3.1.1 Single Word Programming- A.3.1.4 Mass Erase for guidance. 4. urst Programming operations are not applicable to EEPROM 5. Minimum Erase times are achieved under maximum NVM operating frequency fNVMOP. 6. Minimum time, if first word in the array is not blank 7. Maximum time to complete check on an erased block
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A.3.2 NVM Reliability
The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. The failure rates for data retention and program/erase cycling are specified at the operating conditions noted. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. NOTE: All values shown in Table A-12 are target values and subject to further extensive characterization. Table A-12 NVM Reliability Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
1 2
C
NVM Array
Cycles
1000 10,000
Data Retention Lifetime
10 years 10 years
C Flash/EEPROM (-40 to + 85C) C EEPROM (-40 to + 85C)
NOTE: NOTE: NOTE:
Flash cycling performance is 1000 cycles at -40 to +85C. Data Retention is specified for 10 years. EEPROM cycling performance is 10,000 cycles at -40 to +85C. Data retention is specified for 10 years. These figures are provided for commercial quality levels not automotive.
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A.4 Voltage Regulator
The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits. No external DC load is allowed. Table A-13 Voltage Regulator Recommended Load Capacitances
Rating
Load Capacitance on VDD1, 2 Load Capacitance on VDDPLL
Symbol
CLVDD CLVDDPLL
Min
-- --
Typ
220 220
Max
-- --
Unit
nF nF
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A.5 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and Phase-Locked-Loop (PLL).
A.5.1 Startup
Table A-14 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can be found in the HCS12 Clock and Reset Generator (CRG) Block Guide (Motorola document order number, S12CRGV3/D) . Table A-14 Startup Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 2 3 4 5 6 T POR release level T POR assert level
Rating
Symbol
VPORR VPORA PWRSTL nRST PWIRQ tWRS
Min
-- 0.97 2 192 20 --
Typ
-- -- -- -- -- --
Max
2.07 -- -- 196 -- 14
Unit
V V tosc nosc ns tcyc
D Reset input pulse width, minimum input time D Startup from Reset D Interrupt pulse width, IRQ edge-sensitive mode D Wait recovery startup time
A.5.1.1 POR The release level VPORR and the assert level VPORA are derived from the VDD supply. They are also valid if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self clock. The fastest startup time possible is given by nuposc. A.5.1.2 SRAM Data Retention Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset the PORF bit in the CRG Flags Register has not been set. A.5.1.3 External Reset When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an oscillation before reset.
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A.5.1.4 Stop Recovery Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR is performed before releasing the clocks to the system. A.5.1.5 Pseudo Stop and Wait Recovery The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in both modes. The controller can be woken up by internal or external interrupts. After twrs the CPU starts fetching the interrupt vector.
A.5.2 Oscillator
The device features an internal Colpitts oscillator. By asserting the XCLKS input during reset this oscillator can be bypassed allowing the input of a square wave. Before asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start from either power-on, STOP or oscillator fail. tCQOUT specifies the maximum time before switching to the internal self clock mode after POR or STOP if a proper oscillation is not detected. The quality check also determines the minimum oscillator start-up time tUPOSC. The device also features a clock monitor. A Clock Monitor Failure is asserted if the frequency of the incoming clock signal is below the Assert Frequency fCMFA. Table A-15 Oscillator Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 2 3 4 5 6 7 8 9 10 11 12 13
Rating
Symbol
fOSC IOSC nUPOSC tUPOSC tCQOUT fCMFA fEXT tEXTL tEXTH tEXTR tEXTF CIN VDCBIAS
Min
0.5 100 4100 -- 0.45 50 0.5 9.5 9.5 -- -- -- --
Typ
-- -- -- 8(1)
Max
16 -- -- 100(2) 2.5
Unit
MHz A cycOSC ms s KHz MHz ns ns ns ns pF V
C Crystal oscillator range P Startup Current D Oscillator start-up time from POR or STOP C Oscillator start-up time D Clock Quality check time-out P Clock Monitor Failure Assert Frequency P External square wave input frequency(3) D External square wave pulse width low D External square wave pulse width high D External square wave rise time D External square wave fall time D Input Capacitance (EXTAL, XTAL pins) C DC Operating Bias in Colpitts Configuration on EXTAL Pin
100 -- -- -- -- -- 9 1.1
200 50 -- -- 1 1 -- --
NOTES: 1. fosc = 4MHz, C = 22pF. 2. Maximum value is for extreme cases using high Q, low frequency crystals 3. XCLKS =0 during reset
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A.5.3 Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLLs Voltage Controlled Oscillator (VCO) is also the system clock source in self clock mode. A.5.3.1 XFC Component Selection This section describes the selection of the XFC components to achieve a good filter characteristics.
VDDPLL Cs R Phase fosc 1 refdv+1 fref fcmp K Detector Loop Divider 1 synr+1 VCO KV fvco Cp
1 2
Figure A-2 Basic PLL Functional Diagram The following procedure can be used to calculate the resistance and capacitance values using typical values for K1, f1 and ich from Table A-16. The VCO Gain at the desired VCO output frequency is approximated by:
(f - f ) 1 vco --------------------------K 1 1V
K
V
= K e 1
The phase detector relationship is given by:
K = -i ch K V
ich is the current in tracking mode.
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MC9S12A128 Device Guide -- V01.01
The loop bandwidth fC should be chosen to fulfill the Gardner's stability criteria by at least a factor of 10, typical values are 50. = 0.9 ensures a good transient response.
2f f ref 1 ref < ------------------------------------------ ----- f < ------------- ;( = 0.9 ) C 4 50 C 50 + 1 + 2
f
And finally the frequency relationship is defined as
f VCO n = -------------- = 2 ( synr + 1 ) f ref
With the above inputs the resistance can be calculated as:
2nf C R = ----------------------------K
The capacitance Cs can now be calculated as:
2 0.516 2 = ---------------------- -------------- ;( = 0.9 ) s f R f R C C
C
The capacitance Cp should be chosen in the range of:
C 20 C C 10 s p s
The stabilization delays shown in Table A-16 are dependant on PLL operational settings and external component selection (e.g. crystal, XFC filter). A.5.3.2 Jitter Information The basic functionality of the PLL is shown in Figure A-2. With each transition of the clock fcmp, the deviation from the reference clock fref is measured and input voltage to the VCO is adjusted accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency. Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-3.
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MC9S12A128 Device Guide -- V01.01
0
1
2
3
N-1
N
tmin1 tnom tmax1 tminN tmaxN Figure A-3 Jitter Definitions The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (N). Defining the jitter as:
t (N) t (N) max min J ( N ) = max 1 - ---------------------- , 1 - ---------------------- Nt Nt nom nom
For N < 100, the following equation is a good fit for the maximum jitter:
j 1 J ( N ) = ------- + j N2
J(N)
1
5
10
20
N
Figure A-4 Maximum Bus Clock Jitter Approximation This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the effect of the jitter to a large extent.
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Table A-16 PLL Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Rating
Symbol
fSCM fVCO |trk| |Lock| |unl| |unt| tstab tacq tal K1 f1 | ich | | ich | j1 j2
Min
1 8 3 0 0.5 6 -- -- -- -- -- -- -- -- --
Typ
-- -- -- -- -- -- 0.5 0.3 0.2 -120 75 38.5 3.5 -- --
Max
5.5 50 4 1.5 2.5 8 -- -- -- -- -- -- -- 1.1 0.13
Unit
MHz MHz %(1) %(1) %(1) %(1) ms ms ms MHz/V MHz A A % %
P Self Clock Mode frequency D VCO locking range D Lock Detector transition from Acquisition to Tracking mode
D Lock Detection D Un-Lock Detection D Lock Detector transition from Tracking to Acquisition mode
C PLLON Total Stabilization delay (Auto Mode) (2) D PLLON Acquisition mode stabilization delay(2) D PLLON Tracking mode stabilization delay (2) D Fitting parameter VCO loop gain D Fitting parameter VCO loop frequency D Charge pump current acquisition mode D Charge pump current tracking mode C Jitter fit parameter 1(2) C Jitter fit parameter 2(2)
NOTES: 1. % deviation from target frequency 2. fREF = 4MHz, fBUS = 25MHz equivalent fVCO = 50MHz: REFDV = #$03, SYNR = #$018, Cs = 4.7nF, Cp = 470pF, Rs = 10K.
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A.6 SPI
A.6.1 Master Mode
Figure A-5 and Figure A-6 illustrate the master mode timing. Timing values are shown in Table A-17.
SS1 (OUTPUT) 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT)
1. If configured as output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
1 4 4
11
3
12
6 MSB IN2 BIT 6 . . . 1 9 MSB OUT2 BIT 6 . . . 1 LSB OUT LSB IN 10
Figure A-5 SPI Master Timing (CPHA = 0)
SS1 (OUTPUT) 1 2 SCK (CPOL = 0) (OUTPUT) 4 SCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT) PORT DATA
1. If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
12
11
3
4
11
12
6 MSB IN2 BIT 6 . . . 1 10 LSB IN
MASTER MSB OUT2
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
Figure A-6 SPI Master Timing (CPHA =1)
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Table A-17 SPI Master Mode Timing Characteristics1
Conditions are shown in Table A-4 unless otherwise noted, C LOAD = 200pF on all outputs
Num C
1 1 2 3 4 5 6 9 10 11 12 P Operating Frequency
Rating
Symbol
fop tsck tlead tlag twsck tsu thi tv tho tr tf
Min
DC 4 1/2 1/2 tbus - 30 25 0 -- 0 -- --
Typ
-- -- -- -- -- -- -- -- -- -- --
Max
1/4 2048 -- -- 1024 tbus -- -- 25 -- 25 25
Unit
fbus tbus tsck tsck ns ns ns ns ns ns ns
P SCK Period tsck = 1./fop D Enable Lead Time D Enable Lag Time D Clock (SCK) High or Low Time D Data Setup Time (Inputs) D Data Hold Time (Inputs) D Data Valid (after Enable Edge) D Data Hold Time (Outputs) D Rise Time Inputs and Outputs D Fall Time Inputs and Outputs
NOTES: 1. The numbers 7, 8 in the column labeled "Num" are missing. This has been done on purpose to be consistent between the Master and the Slave timing shown in Table A-18.
A.6.2 Slave Mode
Figure A-7 and Figure A-8 illustrate the slave mode timing. Timing values are shown in Table A-18.
SS (INPUT) 1 SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 7 MISO (OUTPUT) SLAVE 5 MOSI (INPUT) MSB IN MSB OUT 6 BIT 6 . . . 1 LSB IN 9 BIT 6 . . . 1 4 4 11 12 8 10 10 12 11 3
SLAVE LSB OUT
Figure A-7 SPI Slave Timing (CPHA = 0)
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MC9S12A128 Device Guide -- V01.01
SS (INPUT) 1 2 SCK (CPOL = 0) (INPUT) 4 SCK (CPOL = 1) (INPUT) 9 MISO (OUTPUT) 7 MOSI (INPUT) SLAVE 5 MSB IN MSB OUT 6 BIT 6 . . . 1 LSB IN 4 11 12 12 11 3
10 BIT 6 . . . 1 SLAVE LSB OUT
8
Figure A-8 SPI Slave Timing (CPHA =1)
Table A-18 SPI Slave Mode Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 200pF on all outputs
Num C
1 1 2 3 4 5 6 7 8 9 10 11 12 P Operating Frequency
Rating
Symbol
fop tsck tlead tlag twsck tsu thi ta tdis tv tho tr tf
Min
DC 4 1 1 tcyc - 30 25 25 -- -- -- 0 -- --
Typ
-- -- -- -- -- -- -- -- -- -- -- -- --
Max
1/4 2048 -- -- -- -- -- 1 1 25 -- 25 25
Unit
fbus tbus tcyc tcyc ns ns ns tcyc tcyc ns ns ns ns
P SCK Period tsck = 1./fop D Enable Lead Time D Enable Lag Time D Clock (SCK) High or Low Time D Data Setup Time (Inputs) D Data Hold Time (Inputs) D Slave Access Time D Slave MISO Disable Time D Data Valid (after SCK Edge) D Data Hold Time (Outputs) D Rise Time Inputs and Outputs D Fall Time Inputs and Outputs
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A.7 External Bus Timing
A timing diagram of the external multiplexed-bus is illustrated in Figure A-9 with the actual timing values shown on table Table A-19. All major bus signals are included in the diagram. While both a data write and data read cycle are shown, only one or the other would occur on a particular bus cycle.
A.7.1 General Muxed Bus Timing
The expanded bus timings are highly dependent on the load conditions. The timing parameters shown assume a balanced load across all outputs.
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MC9S12A128 Device Guide -- V01.01
1, 2 3 ECLK PE4 5 9 Addr/Data (read) PA, PB data 6 16 10 data 7 12 Addr/Data (write) PA, PB data addr 8 14 data 13 4
15 addr
11
17 Non-Multiplexed Addresses PK5:0 20 ECS PK7
18
19
21
22
23
24 R/W PE2
25
26
27 LSTRB PE3
28
29
30 NOACC PE7
31
32
33 IPIPO0 IPIPO1, PE6,5
34
35
36
Figure A-9 General External Bus Timing
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Table A-19 Expanded Bus Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, C LOAD = 50pF
Num C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Rating
Symbol
fo tcyc PWEL PWEH tAD tAV tMAH tAHDS tDHA tDSR tDHR tDDW tDHW tDSW tACCA tACCE tNAD tNAV tNAH tCSD tACCS tCSH tCSN tRWD tRWV tRWH tLSD tLSV tLSH tNOD tNOV
Min
0 40 19 19 -- 11 2 7 2 13 0 -- 2 12 19 6 -- 15 2 -- 11 2 8 -- 14 2 -- 14 2 -- 14
Typ
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max
25.0 -- -- -- 8 -- -- -- -- -- -- 7 -- -- -- -- 6 -- -- 16 -- -- -- 7 -- -- 7 -- -- 7 --
Unit
MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
P Frequency of operation (E-clock) P Cycle time D Pulse width, E low D Pulse width, E high(1) D Address delay time D Address valid time to E rise (PWEL-tAD) D Muxed address hold time D Address hold to data valid D Data hold to address D Read data setup time D Read data hold time D Write data delay time D Write data hold time D Write data setup time(1) (PWEH-tDDW) D Address access time(1) (tcyc-tAD-tDSR) D E high access time(1) (PWEH-tDSR) D Non-multiplexed address delay time D Non-muxed address valid to E rise (PWEL-tNAD) D Non-multiplexed address hold time D Chip select delay time D Chip select access time (1) (tcyc-tCSD-tDSR) D Chip select hold time D Chip select negated time D Read/write delay time D Read/write valid time to E rise (PWEL-tRWD) D Read/write hold time D Low strobe delay time D Low strobe valid time to E rise (PWEL-tLSD) D Low strobe hold time D NOACC strobe delay time D NOACC valid time to E rise (PWEL-tNOD)
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MC9S12A128 Device Guide -- V01.01
Table A-19 Expanded Bus Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, C LOAD = 50pF
Num C
32 33 34 35 36 D NOACC hold time D IPIPO[1:0] delay time
Rating
Symbol
tNOH tP0D tP0V tP1D tP1V
Min
2 2 11 2 11
Typ
-- -- -- -- --
Max
-- 7 -- 25 --
Unit
ns ns ns ns ns
D IPIPO[1:0] valid time to E rise (PW EL-tP0D) D IPIPO[1:0] delay time1 (PWEH-tP1V) D IPIPO[1:0] valid time to E fall
NOTES: 1. Affected by clock stretch: add N x tcyc where N=0,1,2 or 3, depending on the number of clock stretches.
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MC9S12A128 Device Guide -- V01.01
Appendix B Package Information
B.1 General
This section provides the physical dimensions of the MC9S12A128 packages.
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MC9S12A128 Device Guide -- V01.01
B.2 112-Pin LQFP Package
4X PIN 1 IDENT 1 112
0.20 T L-M N
4X 28 TIPS 85 84
0.20 T L-M N
J1 J1 C L
4X
P
VIEW Y
108X
G
X X=L, M OR N
VIEW Y B L M B1 V1 V
J
AA
28
57
F D 0.13
M
BASE METAL
29
56
T
L-M N
N A1 S1 A S
SECTION J1-J1 ROTATED 90 COUNTERCLOCKWISE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M AND N TO BE DETERMINED AT SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B INCLUDE MOLD MISMATCH. 6. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.46. MILLIMETERS MIN MAX 20.000 BSC 10.000 BSC 20.000 BSC 10.000 BSC --1.600 0.050 0.150 1.350 1.450 0.270 0.370 0.450 0.750 0.270 0.330 0.650 BSC 0.090 0.170 0.500 REF 0.325 BSC 0.100 0.200 0.100 0.200 22.000 BSC 11.000 BSC 22.000 BSC 11.000 BSC 0.250 REF 1.000 REF 0.090 0.160 8 0 7 3 13 11 11 13
C2 C 0.050 2
VIEW AB 0.10 T
112X
SEATING PLANE
3 T
R
R2 0.25
GAGE PLANE
R
R1
C1 (Y) (Z) VIEW AB
(K) E
1
DIM A A1 B B1 C C1 C2 D E F G J K P R1 R2 S S1 V V1 Y Z AA 1 2 3
Figure B-1 112-Pin LQFP Mechanical Dimensions (Case no. 987)
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MC9S12A128 Device Guide -- V01.01
B.3 80-Pin QFP Package
L
60 61 41 40
S
S
B B P
D
L
H A-B
B
V 0.05 D
M
M
C A-B
-A-
-B-
S
S
D
0.20
0.20
-A-,-B-,-DDETAIL A
DETAIL A
80 1 20
21
-D0.20
M
F
A H A-B S
S
D
S
0.05 A-B J
S
N
0.20 E C -CSEATING PLANE
M
C A-B
D
S
M DETAIL C -HH G
DATUM PLANE
D 0.20
M
C A-B
S
D
S
SECTION B-B
VIEW ROTATED 90
0.10 M
U T
DATUM PLANE
-H-
R
K W X DETAIL C
Q
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.
DIM A B C D E F G H J K L M N P Q R S T U V W X
MILLIMETERS MIN MAX 13.90 14.10 13.90 14.10 2.15 2.45 0.22 0.38 2.00 2.40 0.22 0.33 0.65 BSC --0.25 0.13 0.23 0.65 0.95 12.35 REF 5 10 0.13 0.17 0.325 BSC 0 7 0.13 0.30 16.95 17.45 0.13 --0 --16.95 17.45 0.35 0.45 1.6 REF
Figure B-2 80-pin QFP Mechanical Dimensions (Case no. 841B)
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MC9S12A128 Device Guide -- V01.01
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User Guide End Sheet
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FINAL PAGE OF 92 PAGES
92

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